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Scrutinizing Layouts:
Team in Mixed Signal Design Kit Department Provides Tools That Validate Layouts and Account for Millions to the Bottom Line

Before a chip goes to production, its layout must be checked to ensure it matches the original design and that it's free of functional flaws. If it's not, millions of dollars go down the drain in discarded material, re-run cycles and lost revenue.

In fact, a recent industry survey shows that half of all chips don't work when the initial prototype comes back from the factory, mainly because of missed bugs.

But thanks in part to the efforts of the Physical Layout Verification and Extraction team, the company has tossed out very few wafers due to layout errors. The team of engineers, part of the Analog and Mixed Signal Department in Platform Technologies, develops software programs to make third-party verification applications work with the company's systems and process technology. The process technologies include digital CMOS, BiCMOS, Bipolar, Gallium Arsenide (GaAs), and flash used to design analog, digital mixed-signal and radio frequency (RF) circuits.

Designers use these applications to scan through the myriad geometric shapes used in a typical chip layout. With the tools, they can extract information to compare the layout with the initial design, verify that the layout is design-rule correct and determine the parasitic effects of metal interconnects - some of which run several meters long. The designers can then accurately predict process yield and identify and correct reliability issues before fabrication begins.

This is no small task. According to a report in Integrated System Design magazine, the databases used for verification are huge and continue expanding to accommodate the decreasing transistor feature sizes -- from 0.25 micron through 0.13 micron and beyond. This circumstance alone is pushing the major workstation manufacturers, such as Sun and Hewlett-Packard, to migrate from 32-bit to 64-bit mega-memory capacity (greater than four gigabytes of RAM).

"Our verification and extraction team has successfully delivered the programs, related scripts, and interfaces for the application tools used for more than 70 in-house or external foundry processes or process variations," says Arya Raychaudhuri, the team's Principal Engineer.

Besides its critical programming function, the team also helps the designers to decipher complex layout errors or mismatches once they are discovered. It's a tall order, considering there are just four members on the team. Besides Arya, the team includes David White, Senior Engineer; Wingsuen Kwan, Engineer; and Venkatesa Ananthan, Engineer.

Arya uses First Awards to honor the achievements of his team members, but he says they have other, stronger motivations. "We work for results," he explains. "If we don't do our best, the projects will be delayed and we will miss the time-to-market bus. This is how we are helping Conexant through this downturn in the semiconductor industry."